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Digital Output, High-Precision Angular Rate Sensor ADIS16130
FEATURES
Low noise density, 0.0125o/sec/Hz Industry-standard serial peripheral interface (SPI) 24-bit digital resolution 250o/sec dynamic range Z-axis, yaw rate response 300 Hz bandwidth, adjustable 35 ms turn-on time Digital self-test High vibration rejection High shock survivability Embedded temperature sensor output Precision voltage reference output 5 V single-supply operation -40C to +85C
GENERAL DESCRIPTION
The ADIS16130 is a low noise, digital output angular rate sensor (gyroscope) that provides an output response over the complete dynamic range of 250o/sec. Its industry-standard serial interface and register structure provide a simple interface that is supported by most MCU, DSP, and FPGA platforms. By implementing a unique design, the device provides superior stability over variations in temperature, voltage, linear acceleration, vibration, and next-level assembly. In addition, the surface-micromachining technology used to manufacture the device is the same high volume BiMOS process used by Analog Devices, Inc., for its high reliability automotive sensor products. Features include a temperature output that provides critical information for system-level calibrations, and a digital self-test feature, which exercises the mechanical structure of the sensor and enables system-level diagnostics. The package configuration is a 36 mm x 44 mm x 16 mm module with a standard 24-lead connector interface.
APPLICATIONS
Guidance and control Instrumentation Inertial measurement units (IMU) Platform stabilization Navigation
FUNCTIONAL BLOCK DIAGRAM
SYNC
ADIS16130
REFERENCE
SYNC
TEMPERATURE SENSOR MEMS ANGULAR RATE SENSOR 2:1 MUX 24-BIT - ADC SERIAL INTERFACE
CS SCLK SDI SDO RDY
SELF-TEST
07238-001
ST
ROA1
ROA2
VCC
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
ADIS16130 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ..............................................8 Basic Operation .................................................................................9 Getting Started Quickly................................................................9 Configuration Options .............................................................. 10 Control Registers ............................................................................ 11 Control Register Details ............................................................ 11 Applications Information .............................................................. 12 Achieving Optimal Noise Performance .................................. 12 Second-Level Assembly ............................................................. 12 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13
REVISION HISTORY
1/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADIS16130 SPECIFICATIONS
TA = 25C, VCC = 5 V, angular rate = 0/sec, COUT = 0 F, 1 g, unless otherwise noted. Table 1.
Parameter SENSITIVITY Dynamic Range 2 Initial Nonlinearity NULL Initial Null In-Run Bias Stability Angle Random Walk Turn-On Time Linear Acceleration Effect Voltage Sensitivity NOISE PERFORMANCE Rate Noise Density 3 FREQUENCY RESPONSE Bandwidth Sensor Resonant Frequency SELF-TEST INPUTS ST RATEOUT Response 4 Logic 1 Input Voltage Logic 0 Input Voltage Input Impedance TEMPERATURE SENSOR Output at 298 K (25C) Scale Factor DIGITAL OUTPUTS Output Low Voltage (VOL) Output High Voltage (VOH) DIGITAL INPUTS Input Current Input Capacitance VT+ VT- (VT+) - (VT-) POWER SUPPLY Operating Voltage Range Quiescent Supply Current TEMPERATURE RANGE Operating Range
1 2
Conditions Clockwise rotation is positive output (See Figure 5) Full-scale range over specified operating conditions Best fit straight line 1 1 1 Power on to 0.5/sec of final value, 80 Hz bandwidth Any axis VCC = 4.75 V to 5.25 V
Min 1 250 22,548
Typ
Max
Unit /sec LSB//sec % of FS /sec /sec /hr ms /sec/g /sec /V /sec/Hz Hz kHz
23,488 0.04 3 0.0016 0.56 35 0.05 0.2 0.0125
24,428
-3 dB frequency with no external capacitance
300 14 65 3.3 75 85 1.7 3.13 8,388,608 14,093 0.4 4
ST pins from Logic 0 to Logic 1 Standard high logic level definition Standard low logic level definition To GND
/sec V V k LSB LSB/C V V A A pF V V V V mA C
CS All others 5 1.4 0.8 0.3 4.75 IOUT = 0 mA, 5 V -40 5.00 73
10 1 2 1.4 0.85 5.25 85 +85
All minimum and maximum specifications are guaranteed. Typical specifications are not tested or guaranteed. Dynamic range is the maximum full-scale measurement range possible, including output swing range, initial offset, sensitivity, offset drift, and sensitivity drift at 4.75 V to 5.25 V supplies. 3 Resulting bias stability is <0.01/sec. 4 Self-test response varies with temperature, see Figure 12.
Rev. 0 | Page 3 of 16
ADIS16130
TIMING SPECIFICATIONS
All input signals are specified with 10% to 90% rise and fall times of less than 5 ns. Table 2.
Parameter t1 Read Operation t4 t5 1 t5A1, 2 t6 t7 t8 t9 3 Write Operation t11 t12 t13 t14 t15 t16
1 2
Min 50 0 0 0 50 50 0 10 0 30 25 50 50 0
Typ
Max
Unit ns ns
Test Conditions/Comments SYNC pulse width CS falling edge to SCLK falling edge setup time SCLK falling edge to data valid delay DVDD of 4.75 V to 5.25 V CS falling edge to data valid delay DVDD of 4.75 V to 5.25 V SCLK high pulse width SCLK low pulse width CS rising edge after SCLK rising edge hold time Bus relinquish time after SCLK rising edge CS falling edge to SCLK falling edge setup Data valid to SCLK rising edge setup time Data valid after SCLK rising edge hold time SCLK high pulse width SCLK low pulse width CS rising edge after SCLK rising edge hold time
60 60
ns ns ns ns ns ns ns ns ns ns ns ns
80
These numbers are measured with the load circuit shown in Figure 4 and defined as the time required for the output to cross the VOL or VOH limits. This specification is relevant only if CS goes low while SCLK is low. 3 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 4. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. Therefore, the times quoted are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
Rev. 0 | Page 4 of 16
ADIS16130
CS
t11
SCLK
t14
t16
t12 t13
SDI MSB
t15
LSB
Figure 2. Input Timing for Write Operation
CS
t4
SCLK
t6
t8
t5 t5A
SDO MSB
t7 t9
LSB
07238-003
Figure 3. Output Timing for Read Operation
ISINK (800A AT DVDD = 5V 100A AT DVDD = 3V) TO OUTPUT PIN 50pF ISOURCE (200A AT DVDD = 5V 100A AT DVDD = 3V)
07328-024
1.6V
Figure 4. Load Circuit for Access Time and Bus Relinquish Time
Rev. 0 | Page 5 of 16
07238-002
ADIS16130 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Acceleration (Any Axis, Unpowered, 0.5 ms) Acceleration (Any Axis, Powered, 0.5 ms) +VS Output Short-Circuit Duration (Any Pin to Common) Operating Temperature Range Storage Temperature Range Rating 2000 g 2000 g -0.3 V to +6.0 V Indefinite -40C to +85C -65C to +150C
THERMAL RESISTANCE
The ADIS16130 provides a temperature output that is representative of the junction temperature. This can be used for system-level monitoring and power management/thermal characterization. Table 4. Thermal Characteristics
Package Type1 24-Lead Module
1
JA 15.7
JC 1.48
Unit C/W
Weight = 28.5 g typical.
RATE AXIS POSITIVE ROTATION DIRECTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Dropping the device onto a hard surface may cause a shock of greater than 2000 g and exceed the absolute maximum rating of the device. Care should be exercised when handling the device to avoid damage.
+
Figure 5. Rotational Measurement Orientation
ESD CAUTION
Rev. 0 | Page 6 of 16
07238-026
ADIS16130 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADIS16130
TOP VIEW (Not to Scale)
2
4
6
8
10
12
14
16
18
20
22
24
1
ST
3
ST
5
ST
7
ST
9
ST
11
VCC
13
VCC
15
VCC
17
GND
19
GND
21
GND
23
ROA1
07328-004
Figure 6. Pin Configuration, Top View
Table 5. Pin Function Descriptions
Pin No. 1 to 7, 9 8 10 11, 13, 15 12 14 16 17, 19 to 22 18 23 24 Mnemonic ST CS RDY VCC SDO SDI SCLK GND SYNC ROA1 ROA2 Description Self-Test (see the Self-Test Function section) Chip Select of the SPI Data Ready Power Supply Data Output of the SPI Data Input of the SPI Serial Clock of the SPI Power Supply Ground Synchronization Input Analog Filter Node 1 Analog Filter Node 2
Rev. 0 | Page 7 of 16
ROA2
SYNC
SCLK
GND
GND
SDO
RDY
SDI
CS
ST
ST
ST
ADIS16130 TYPICAL PERFORMANCE CHARACTERISTICS
2.5 2.0 ROOT ALLEN VARIANCE (/sec) 1.5 BIAS SHIFT (/sec) 1.0 0.5 0 -0.5 -1.0 -1.5
07328-018
0.010
+ - 0.001 1 10 (sec) 100
07328-021
-2.0 -2.5 -60 -40 -20 0 20 40 60 80 100
120
1000
TEMPERATURE (C)
Figure 7. Bias Shift vs. Temperature, VCC = 5 V
Figure 10. Root Allen Variance, VCC = 5 V, 25C
1.00 0.75 SENSITIVITY ERROR (%)
2.0
0.25 0 -0.25 -0.50
07328-019
SENSITIVITY ERROR (%)
0.50
1.0
0
-1.0
07328-022
-0.75 -1.00 -60
-40
-20
0
20
40
60
80
100
120
-2.0
0
50
100
150
200
250
300
350
400
TEMPERATURE (C)
ANGULAR RATE (/sec)
Figure 8. Sensitivity Error vs. Temperature, VCC = 5 V
Figure 11. Sensitivity Error vs. Angular Rate, VCC = 5 V, 25C
0.05
90
85 SENSITIVITY ERROR (%) 0
SELF-TEST RESPONSE (/sec)
07328-020
80
-0.05
75
70
-0.10
65
07328-023
-0.15
4.75
5.0 POWER SUPPLY (V)
5.25
60 -60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 9. Sensitivity Error vs. Power Supply, 25C
Figure 12. Self-Test Response vs. Temperature, VCC = 5 V
Rev. 0 | Page 8 of 16
ADIS16130 BASIC OPERATION
The ADIS16130 produces digital angular rate (RATE) and temperature (TEMP) data. The digital communication employs a simple 4-wire SPI, which provides access to output data and several configuration features. A set of communication and configuration registers govern the operation in the ADIS16130. See Table 8 for a summary of these registers. Figure 13 provides an example read sequence, and Table 2 and Figure 3 provide critical timing details for the output signal. The first byte of the sequence uses SDI to establish a read of the RATE output register. This is accomplished by writing 0x48 to the COM register. The most significant byte is first in the SDO sequence, followed by the next significant, and then the least significant. When 16-bit resolution is in use, only two bytes are output from the SDO during the read sequence.
CS SCLK SDO SDI RDY 0x48
07328-005
GETTING STARTED QUICKLY
The ADIS16130 SPI operates in 8-bit segments. The first byte of a SPI sequence goes into the COM register, which contains the read/write control bit and the address of the target register. When writing information into control registers, the next byte contains the configuration information. When reading output data, the next one to three bytes contain the contents of the register selected.
DATA
DATA
DATA
Configuration Sequence
The sequence in Table 6 provides the recommended configuration sequence. Table 2 and Figure 2 provide the timing information for each segment of this configuration sequence. Table 6. Configuration Sequence
Step 1 2 SDI1 0x01 0x38 Register COM IOP Purpose Start a write sequence for IOP. Configure the data-ready signal to pulse low when the RATEDATA and TEMPDATA output registers contain new data. The data-ready signal goes high after reading either of these registers. Start a write sequence for the RATECS register. Enable and configure the gyroscope data channel. Start a write sequence for RATECONV register. Initialize the RATE conversion. Start a write sequence for the TEMPCS register. Enable and configure the temperature data channel. Start a write sequence for TEMPCONV. Initialize the TEMP conversion. Start a write sequence for the MODE register. Establish the data output resolution to 24 bits and start the conversion process with the RATEDATA channel.
Figure 13. Read Sequence Example
3 4 5 6 7 8 9 10 11 12
0x28 0x0A 0x30 0x05 0x2A 0x0A 0x32 0x05 0x38 0x22
COM RATECS COM RATECONV COM TEMPCS COM TEMPCONV COM MODE
The data-ready signal, RDY, indicates that unread data is available on both RATE and TEMP output registers. After the RATE or TEMP channel is read, the signal returns high, as shown in Figure 13. The RATE and TEMP channels update sequentially, and each has a sample rate of 5.7 kSPS. The internal sample rate is not dependent on the SPI signals or read rates. Using the data-ready signal to drive data collection helps avoid losing data due to data collision, which is when a userdriven read cycle coincides with the internal update time. In this case, the old data remains and the new data is lost. If a lower sample rate meets system-level requirements, the data-ready signal can still be useful in facilitating SPI read sequences. In this case, the data-ready signal pulses high for approximately 26 s before returning low and then repeats this pattern at two times the internal sample rate. This signal can feed a counter circuit (or firmware), which drives a processor interrupt routine at a reduced sample rate.
Reading TEMP Output Data
Reading TEMP data requires a sequence that is very similar to that of Figure 13, except that the initial SDI sequence must be changed from 0x48 to 0x4A. If the TEMP data is not used, Step 7 to Step 10 of the configuration sequence are not required.
1
The SDI column lists the hexadecimal code representation of the SDI bit input sequence.
Reading RATE Output Data
After the configuration sequence in Table 6 is complete, reading the output data is very simple. The ADIS16130 converts the RATE and TEMP data continuously. To better understand this process,
Rev. 0 | Page 9 of 16
ADIS16130
CONFIGURATION OPTIONS
Synchronization Input
The SYNC pin can be used to synchronize the ADIS16130 with other devices in the system. When the SYNC bit in the I/O port register (IOP) is set and the SYNC pin is low, the ADIS16130 does not process any conversions. Instead, it waits until the SYNC pin goes high, and then starts the operation. This allows the conversion to start from a known point in time (for example, the rising edge of the SYNC pin).
0 -1 -2 -3
AMPLITUDE (dB)
327Hz
1kHz
Figure 14. Frequency Response Block Diagram
Cext = 0.15F
-4 -5 -6 -7 -8 -9 -10 1
Cext = 0F
Self-Test Function
The self-test function enables system-level diagnostic checks for the entire ADIS16130 sensor/signal conditioning circuit. To activate the self-test function, there must be a logic high signal on all ST pins (see Table 5). When activated, the self-test function results in a rate measurement shift. By comparing the observed shift with the limits specified in this data sheet, users can determine the pass/fail criteria for system-level diagnostic routines. For normal gyroscope operation, place a logic low input on all ST pins. For systems that do not require this feature, tie all ST pins to GND.
07328-006
ADC
10
100 FREQUENCY (Hz)
1k
10k
Figure 15. Frequency Response: Cext = 0 F vs. Cext = 0.15 F
Table 7. Nominal Bandwidth for Standard Capacitor Values
Cext (pF) 1000 1200 1500 1800 2200 2700 3300 3900 4300 4700 5100 5600 6200 7500 8200 9100 BW (Hz) 276.8 274.4 270.9 267.5 263.1 257.7 251.6 245.8 242.1 238.4 234.9 230.7 225.8 215.8 210.8 204.7 Cext (pF) 10,000 12,000 15,000 18,000 22,000 27,000 33,000 39,000 43,000 47,000 51,000 56,000 62,000 75,000 82,000 91,000 BW (Hz) 198.9 187.2 172.1 159.2 144.7 129.9 115.7 104.4 97.9 92.3 87.2 81.6 75.8 65.6 61.2 56.3 Cext (pF) 100,000 120,000 150,000 180,000 220,000 270,000 330,000 390,000 430,000 470,000 510,000 560,000 620,000 750,000 820,000 910,000 BW (Hz) 52.2 44.8 37.0 31.5 26.3 21.8 18.1 15.5 14.1 12.9 12.0 10.9 9.9 8.2 7.6 6.8
Analog Bandwidth
The typical -3 dB cutoff frequency for the ADIS16130 is 300 Hz, which is the combined response of two single-pole filters, as shown in Figure 14. Pin ROA1 and Pin ROA2 provide the opportunity for further bandwidth reduction in the first filter stage, as shown in the following relationship:
f -3dB =
1 2 x x R x (C + C ext )
where: R = 25 k. C = 6800 pF. Cext is as defined in Figure 15 and Table 7. The relationship between the -3 dB cutoff frequency and the external capacitance of the ADIS16130 is shown in Table 7 and Figure 15.
Rev. 0 | Page 10 of 16
07328-007
ADIS16130 CONTROL REGISTERS
Table 8. Register Descriptions
Name COM IOP RATEDATA TEMPDATA RATECS TEMPCS RATECONV TEMPCONV MODE Address 0x00 0x01 0x02 to 0x07 0x08 0x0A 0x10 to 0x22 0x28 0x2A 0x30 0x32 0x33 to 0x37 0x38 Type W R/W R R R/W R/W R/W R/W R/W Purpose Facilitate communications in the SPI port (see Table 9) Data-ready and synchronization controls (see Table 10) Reserved Gyroscope output, rate of rotation (see Figure 13) Temperature output (see Figure 13) Reserved Gyroscope channel setup (see Table 11) Temperature channel setup (see Table 12) Gyroscope conversion time control (see Table 13) Temperature conversion time control (see Table 13) Reserved Resolution mode control (see Table 14)
CONTROL REGISTER DETAILS
Table 9. COM Register Bit Assignments
Bit [7] [6] [5:0] Description 0 1 = read; 0 = write Register address
Table 12. TEMPCS Register Bit Assignments
Bit [7:4] [3] [2:0] Description 0000 1 = channel enable; 0 = channel disable 010
Table 10. IOP Register Bit Assignments
Bit [7:4] [3] [2:1] [0] Description 0011 1 = data-ready signal low when unread data on all channels; 0 = data-ready signal low when unread data on one channel 00 0 = synchronization disabled; 1 = synchronization enabled
Table 13. RATECONV/TEMPCONV Bit Assignments
Bit [7:0] Description 00000101
Table 14. MODE Register Bit Assignments
Bit [7:2] [1] [0] Description 001000 1 = 24-bit resolution; 0 = 16-bit resolution 0
Table 11. RATECS Register Bit Assignments
Bit [7:4] [3] [2:0] Description 0000 1 = channel enable; 0 = channel disable 010
Rev. 0 | Page 11 of 16
ADIS16130 APPLICATIONS INFORMATION
ACHIEVING OPTIMAL NOISE PERFORMANCE
Several system-level considerations can have an impact on the noise and accuracy of the ADIS16130. Understanding and managing these factors can influence the behavior of any high performance system.
15.600 BSC 31.200 BSC
Supply and Common Considerations
The ADIS16130 provides approximately 1.8 F of decoupling capacitance. This capacitance is distributed throughout the device and should be taken into account when considering potential noise threats on the power supply lines.
39.60 BSC 19.800 BSC 17.520
2x 0.560 BSC ALIGNMENT HOLES FOR MATING SOCKET
2.280
4x 2.500 BSC 5.00 BSC
5.00 BSC
If COUT is applied to reduce the bandwidth of the ADIS16130 response, it should be placed close to the device. Long cable leads and PCB traces increase the risk of introducing noise into the system.
Figure 16. Suggested Hole Pattern for Mounting
SECOND-LEVEL ASSEMBLY
The ADIS16130 package supports two mounting approaches: a bulkhead mount, where the interface is separate from the attachment surface, and a PCB mount, which provides the mechanical and electrical connections on the same surface. Figure 16 provides a suggested design for the ADIS16130's mechanical attachment. The hole pattern shown in Figure 16 can support either mounting approach and enables the integration of the mating socket layout, which is illustrated in Figure 17. The mating socket layout uses the Samtec CLM-112-02 family of connectors. The 24 holes that are inside the pad accommodate the pins on the ADIS16130, which can extend beyond the package body. The stress relief provided by these holes is important for maintaining reliability and optimal bias stability performance.
0.4334 [11.0] 0.019685 [0.5000] (TYP) 0.0240 [0.610]
0.054 [1.37] 0.0394 [1.00] 0.1800 [4.57]
Figure 17. Mating Socket Recommended Pad Layout, with Dimensions Shown in Inches (Millimeters)
Rev. 0 | Page 12 of 16
07328-017
0.022 DIA (TYP) NONPLATED 0.022 DIA THRU HOLE (TYP) THRU HOLE 2x NONPLATED THRU HOLE
0.0394 [1.00]
07238-025
Bandwidth Setting
ADIS16130 OUTLINE DIMENSIONS
35.854 35.600 35.346
31.350 31.200 31.050 15.700 15.600 15.500
2.200 TYP
2.400 THRU HOLE (4 PLACES)
17.670 17.520 17.370 39.750 39.600 39.450
44.254 44.000 43.746
19.900 19.800 19.700
TOP VIEW 14.054 13.800 13.546
2.200 TYP
END VIEW
3.27 3.07 2.87 1.00 BSC (LEAD PITCH) 5.50 BSC 0.30 BSC SQ (PIN SIZE)
010908-A
Figure 18. PCB Module with Connector Interface (ML-24-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADIS16130AMLZ 1
1
Temperature Range -40C to +105C
Package Description PCB Module with Connector Interface
Package Option ML-24-3
Z = RoHS Compliant Part.
Rev. 0 | Page 13 of 16
ADIS16130 NOTES
Rev. 0 | Page 14 of 16
ADIS16130 NOTES
Rev. 0 | Page 15 of 16
ADIS16130 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07238-0-1/08(0)
Rev. 0 | Page 16 of 16

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